H - Electricity – 04 – J
Patent
H - Electricity
04
J
H04J 3/06 (2006.01) H04J 3/12 (2006.01) H04J 3/14 (2006.01) H04L 7/00 (2006.01)
Patent
CA 2088210
Abstract The present invention relates to a process for synchronizing the circuit elements of a digital telecommunications systems, with at least one central clock system that is connected to the synchronizing and clock pulse failure monitoring devices of the circuit elements through a bit pulse line and a frame pulse line. A first, predetermined, sequence of signal states that is generated by the clock and sent out on the frame pulse line, and which is at least two bits long, is identified by the synchronizing devices of the circuit elements that are to be synchronized as a frame synchronous word; and in that a second sequence of alternating signal states is transmitted between sequential frame synchronous words, this being different from the first predetermined sequence and serving to post-trigger the clock pulse failure monitoring devices. This leads to a more frequent change of state on the frame pulse line, and this can be utilized by the clock pulse failure monitoring devices in order to identify drop-out or error more rapidly.
Aktiengesellschaft Siemens
Diekmann Thomas
Fetherstonhaugh & Co.
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