Process and device for testing an integrated circuit...

Details Process and device for testing an integrated circuit... Process and device for testing an integrated circuit...

G - Physics

01

R

G01R 31/04 (2006.01) G01R 31/317 (2006.01) G01R 31/319 (2006.01)

Patent

CA 2164415

Test system as well as method for testing for the proper connection of the pins of an IC connected to the circuit tracks of a circuit board, by measurements on parasitic transistors with correction of the detected collector currents in respect of the additional diode-connected parallel transistors in CMOS-IC's.

L'invention concerne un procédé et un dispositif de test permettant de vérifier si la connexion entre les broches d'un circuit intégré brasé et les tracés conducteurs d'une platine est correcte, en mesurant les transistors parasites pour corriger les courants de collecteur mesurés concernant les transistors additionnels montés en parallèle par l'intermédiaire d'une diode dans les circuits intégrés CMOS, le collecteur de ces transistors se trouvant sur la broche de tension d'alimentation.

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