Process for fabricating integrated circuits having shallow...

Details Process for fabricating integrated circuits having shallow... Process for fabricating integrated circuits having shallow...

H - Electricity

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356/151

H01L 21/60 (2006.01) H01L 21/285 (2006.01) H01L 21/768 (2006.01)

Patent

CA 1314631

- 11 - Abstract For integrated circuit devices with strict design rules, junctions defining the source and drain are typically more shallow than 0.25 µm and aremade through vias having an aspect ratio greater than 1.1. Suitable electrical contact to such a shallow junction is quite difficult. To ensure an appropriate contact, an adhesion barrier layer such as titanium nitride or an alloy of titanium and tungsten is first deposited. Tungsten is then deposited under conditions which produce a self-limiting effect in a prototypical deposition on silicon. Additionally, these tungsten deposition conditions are adjusted to higher rather than lower deposition temperatures. Subsequent deposition of aluminum if desired, completesthe contact.

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