Process for fabricating multilevel metal integrated circuits...

Details Process for fabricating multilevel metal integrated circuits... Process for fabricating multilevel metal integrated circuits...

H - Electricity

01

L

356/141

H01L 23/532 (2006.01) H01L 21/768 (2006.01)

Patent

CA 1264379

Abstract The specification describes a multilevel metal CMOS integrated circuit wherein a first or lower level of metallization comprises strips of tungsten over aluminum. These strips are connected through vias in an inter-metal dielectric layer to an upper or second level of metallization which is photodefined in a desired pattern. The tungsten suppresses hillocks in the underlying aluminum during high temperature processing and also advantageously serves as an etch stop material during integrated circuit fabrication.

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