Process for fabricating self-aligned silicide lightly doped...

Details Process for fabricating self-aligned silicide lightly doped... Process for fabricating self-aligned silicide lightly doped...

H - Electricity

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356/128

H01L 21/28 (2006.01) H01L 21/033 (2006.01) H01L 21/336 (2006.01) H01L 21/60 (2006.01) H01L 29/78 (2006.01)

Patent

CA 1294061

ABSTRACT In a method for fabricating an MOS structure, in accordance with one embodiment, a layer of material that serves as an etching stop during the side wall spacer etch, is inserted between the silicon substrate and the side wall spacer. In another embodiment of the invention, after establishing differential layer thicknesses on the source/drain surface, the side wall spacer is completely removed and light and heavy ion implantation steps are performed sequentially with one single lithographic step. In a further embodiment of the invention, after the self-aligned silicide is formed, the side wall spacer is removed, and light and heavy ion implantation steps are sequentially performed.

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