H - Electricity – 01 – L
Patent
H - Electricity
01
L
356/179
H01L 21/22 (2006.01) H01L 21/225 (2006.01)
Patent
CA 1194616
- 14- METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE Abstract A method for forming a shallow and highly concentrated arsenic doped surface layer in a silicon bulk region includes the steps of forming an arsenic doped polysilicon layer in contact with a preselected area of a bulk region surface in which the surface layer is to be formed and completely oxidizing the polysilicon layer at a rate exceeding the rate at which arsenic diffuses in the bulk region. Since arsenic has a relatively high silicon/silicon dioxide segregation coefficient and the oxidation rate exceeds the arsenic diffusion rate, arsenic accumulates at the silicon dioxide/silicon interface during oxidation, and nearly all of the arsenic in the region of the polysilicon layer above the preselected area is driven into the bulk region surface by the oxidation to form an impurity layer having a very high surface concentration of arsenic.
421500
Kirby Eades Gale Baker
Western Electric Company Incorporated
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