Process for forming complementary integrated circuit devices

Details Process for forming complementary integrated circuit devices Process for forming complementary integrated circuit devices

H - Electricity

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H01L 21/28 (2006.01) H01L 21/265 (2006.01) H01L 21/266 (2006.01) H01L 21/8238 (2006.01) H01L 29/06 (2006.01) H01L 27/092 (2006.01)

Patent

CA 1194612

Abstract: The present invention relates to a process used in the manufacture of CMOS integrated circuits. The process involves the steps of forming in a silicon wafer, contiguous surface regions of opposite conductivity types. The process involves the forming of islands of composite layers of silicon nitride and silicon oxide over various portions of the surface regions. The process further includes the step of implanting boron selectively into the surface regions of both conductivity types not covered by the islands and covering the p-type surface regions with an implantation mask. Ions are then implanted from the group consisting of arsenic and phosporous selectively into the n-type surface regions not covered by the ions, the dosage being substantially the same for both implantations. The implantation mask is then removed from the p-type surface regions. The wafer is then heated in an oxidizing atmosphere for oxidizing the surface regions not covered by ions and forming under the oxidized regions p-type chanstops in the p-type surface regions and n-type chanstops in the n-type surface regions. The islands are then removed. The final step of the process involves forming n-type MOS transistors in the p-type surface regions and p-type MOS transistors in the n type surface regions previously covered by islands.

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