Process for forming ldd mos/cmos structures

H - Electricity – 01 – L

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H01L 21/265 (2006.01) H01L 21/8238 (2006.01) H01L 29/78 (2006.01)

Patent

CA 1256588

PROCESS FOR FORMING LDD MOS/CMOS STRUCTURE Abstract of the Disclosure A process for selectively forming NMOS/PMOS/CMOS integrated circuits and for selectively incorporating any or all of lightly doped drain-source (LDD) regions, sidewall gate oxide structures, and guard band regions.

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