H - Electricity – 01 – L
Patent
H - Electricity
01
L
356/136
H01L 21/768 (2006.01) G03F 7/09 (2006.01) H01L 21/027 (2006.01)
Patent
CA 1244145
Abstract of the Disclosure Disclosed is a process of forming high density, planar, single- or multi-level wiring for an semicon- ductor integrated circuit chip. On the chip surface is provided a dual layer of an insulator and hardened photoresist having various sized openings (grooves for wiring and openings for contacts) therein in a pattern of the desired wiring. A conductive (e.g., metal) layer of a thickness equal to that o. the insulator is deposited filling the grooves and contact openings. A sacrificial dual (lower and upper component) layer of (hardened) photoresist is formed filling the metal valleys and obtaining a substantially planar surface. The lower component layer is thin and conformal and has a higher etch rate than the upper component layer which is thick and nonconformal. By reactive ion etching the sacrificial layer is removed leaving resist plugs in the metal valleys. Using the plug as etch masks, the exposed metal is removed followed by removal of the remaining hardened photoresist layer and the plugs leaving a metal pattern coplanar with the insulator layer. This sequence of steps is repeated for multilevel wiring. When only narrow wiring is desired, a single photoresist layer is substituted for the dual photo- resist sacrificial layer.
529470
Balasubramanyam Karanam
Dally Anthony J.
Ogura Seiki
Riseman Jacob
International Business Machines Corporation
Saunders Raymond H.
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