Process for forming vias on integrated circuits

Details Process for forming vias on integrated circuits Process for forming vias on integrated circuits

H - Electricity

01

L

356/136

H01L 21/768 (2006.01) H01L 21/3213 (2006.01)

Patent

CA 1249072

Abstract In a process of forming vias for multilevel interconnects used in integrated circuits, a layer of a first metal is formed on a semiconductor substrate. A layer of a second metal is formed on the first metal layer. The second metal layer is etched in a predetermined via pattern with second etchant which reacts with the second metal and which is substantially unreactive with the first metal. The first metal layer is then etched with a first etchant which reacts with the first metal and which is substantially unreactive with the second metal or with the semiconductor substrate in order to form a predetermined contacting relationship with the predetermined via pattern. This process may be used to generate second and subsequent levels of vias and interconnects which can be used to contact metal layers at any level directly to the substrate by building via posts from the substrate to any desired metal layer.

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