Process for managing a plurality of electronic smart token...

Details Process for managing a plurality of electronic smart token... Process for managing a plurality of electronic smart token...

G - Physics

06

K

G06K 7/016 (2006.01) G01V 3/12 (2006.01) G01V 15/00 (2006.01) G06K 19/07 (2006.01) G07D 9/00 (2006.01) A44C 21/00 (2006.01)

Patent

CA 2529134

A method for managing in a consistent manner a plurality (12) of contactless radiofrequency readers (12a,12b,12c) for reading tokens (15a,15b,15c) provided with electronic chips (16) in the form of a transmitting/receiving Tx/Rx cycle consist in transmitting Tx a reader instruction to the chips, in subsequently receiving Rx the response of the chips (16) to the reader (12a,12b,12c) and in synchronising the cycles Tx/Rx in such a way that the transmissions Tx are bunched in a first time interval and the receptions Rx are bunched in a second time interval without overlapping between said two time intervals. The readers (12a,12b,12c) are coupled to a synchronisation circuit (20) provided with a microprocessor processing circuit (22) and to an interface circuit (24) connected to each reader (12a,12b,12c), in particular, for transmitting clock signals synchronised by the microproccesor circuit (22) thereto.

Le procédé de gestion coordonnée d'une pluralité (12) de lecteurs (12a,12b,12c) radiofréquence sans contact de jetons (15a,15b,15c) à puce électronique (16) du type à cycle de transmission/réception Tx/Rx comportant la transmission Tx d'une commande du lecteur vers les puces suivie de la réception Rx de la réponse des puces (16) vers le lecteur (12a,12b,12c), comprend une synchronisation des cycles Tx/Rx de façon à grouper dans un premier intervalle de temps les transmissions Tx et à grouper dans un second intervalle de temps les réceptions Rx sans chevauchement entre les deux intervalles de temps. Les lecteurs (12a,12b,12c) sont associés à un circuit de synchronisation (20) comportant un circuit de traitement à microprocesseur (22) et un circuit d'interface (24) relié à chacun des lecteurs (12a,12b,12c), notamment pour délivrer à ceux-ci des signaux d'horloge synchronisés par le circuit à microprocesseur (22).

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