H - Electricity – 01 – L
Patent
H - Electricity
01
L
H01L 21/02 (2006.01) H01L 21/28 (2006.01) H01L 21/60 (2006.01) H01L 21/78 (2006.01) H01L 23/48 (2006.01) H01L 23/482 (2006.01) H01L 23/485 (2006.01) H01L 23/50 (2006.01) H01L 23/52 (2006.01)
Patent
CA 2159242
A process for manufacturing a semiconductor device. Chip sections are defined on a wafer by scribe lines, with each chip section having chip electrodes formed thereon. The wafer is covered with a passivating film except for an area on the chip electrodes. Aluminum interconnection layers are provided such that each layer is connected to the chip electrode at one end thereof, and the other end of the layer is extended towards the central portion of the chip section. A cover coating film is applied on the passivating film and the layers. A number of apertures are formed in the coating film passing therethrough, and bump electrodes are formed at the position corresponding to the apertures. The chip sections are then separated from each other along the scribe lines into semiconductor devices.
Chikaki Shinichi
Kata Keiichiro
G. Ronald Bell & Associates
Nec Electronics Corporation
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