H - Electricity – 05 – K
Patent
H - Electricity
05
K
356/17, 96/252
H05K 1/00 (2006.01) H05K 3/18 (2006.01) H05K 3/46 (2006.01)
Patent
CA 1262577
PROCESS FOR PREPARING MULTILAYER PRINTED CIRCUIT BOARDS ABSTRACT Multilayer printed circuit boards are fabricated by preparing a first layer in conventional manner by forming a resist image on a copper clad substrate, etching away unwanted copper, removing the resist from the circuit pattern and optionally applying a dielectric mask such as conventional solder mask to selected portions of the cir- cuit pattern. A second layer, and optionally one or more subsequent layers, are fabricated by providing an image of a second circuit pattern in a predetermined location on said first layer, the image being formed using a sus- pension of cuprous oxide in a curable resin material. The image is cured at least partially and subjected to chemical reduction to convert at least a portion of the cuprous oxide to metallic copper. The image is then electrolessly plated with copper to build up the circuit pattern and the latter is selectively coated with a dielectric mask before repeating the cycle to build up one or more additional layers. Solder can be applied to selected areas of any of said printed circuit layers at any appropriate time during fabrication. The above method of fabrication has advantages of economy of time, materials and labor as compared with methods hitherto employed to prepare multilayer boards in which a plurality of single boards are fabricated indivi- dually and then assembled as a sandwich or laminate by application of heat and pressure.
547294
Castaldi Steven A.
Ferrier Donald R.
Gallegos Daniel
Larson Gary B.
Ruszczyk Stanley J.
Castaldi Steven A.
Ferrier Donald R.
Gallegos Daniel
Larson Gary B.
Macdermid Incorporated
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