Process for producing a multi-chip wiring arrangement

Details Process for producing a multi-chip wiring arrangement Process for producing a multi-chip wiring arrangement

H - Electricity

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H05K 3/12 (2006.01) H01L 21/60 (2006.01) H05K 3/24 (2006.01) H05K 3/34 (2006.01) H05K 1/03 (2006.01) H05K 3/06 (2006.01) H05K 3/10 (2006.01) H05K 3/38 (2006.01)

Patent

CA 1039855

ABSTRACT A process for producing multi-chip wiring which facilitates high packing density and reliable flip-chip connections. In the process, an adhesive layer and a contact layer are vapor deposited onto a carrier. The desired structure of the connector path, outer contacts and connection surfaces are covered with a conductive layer and an intermediate layer with the aid of a first photo-laquer mask by galvanic metal deposition. A solder-rejecting layer is galvanically deposited onto the structure of the conductor paths with the aid of a second photo-lacquer mask. The undesired regions of the adhesive layer and of the contact layer are etched away and the outer contacts and connection surfaces are covered with a solderable contact layer by selective currentless metal deposition.

235059

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