H - Electricity – 01 – L
Patent
H - Electricity
01
L
356/177
H01L 21/316 (2006.01) G03C 5/00 (2006.01) G03F 7/09 (2006.01) H01L 21/3105 (2006.01) H01L 21/311 (2006.01) H01L 21/3213 (2006.01) H01L 21/762 (2006.01)
Patent
CA 1159966
Improved Process of Forming Recessed Dielectric Regions In A Monocrystalline Silicon Substrate Abstract A method of forming surface planarity to a substrate during removal of excess dielectric material when fabricating recessed regions of dielectric material in a semiconductor device wherein a dielectric layer is formed on the surface of the silicon sub- strate, a relatively thick layer of polycrystalline silicon deposited over the SiO2 layer, openings formed through the polycrystalline layer and SiO2 layer and into the substrate to form trenches, vapor depositing a layer of dielectric material over the surface of the substrate to a depth sufficient to fill the trench, depositing a planarized layer over a layer of dielectric material, reactive ion etching the planarizing layer, the dielectric layer, the polycrystalline layer, and selectively removing the remaining polycrystalline silicon layer to expose the SiO2 layer.
381235
International Business Machines Corporation
Saunders Raymond H.
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