Process, voltage, temperature independent switched delay...

H - Electricity – 03 – K

Patent

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Details

H03K 5/14 (2006.01) H03K 5/159 (2006.01) H03L 7/081 (2006.01) H03L 7/089 (2006.01)

Patent

CA 2596269

A circuit for modeling a course delay element with a plurality of fine delay elements. The circuit includes first and second delay paths, each including a plurality of delay elements for receiving a clock signal. A phase detector detects a phase difference between the delayed clock signal provided from the first and second delay paths, which is provided to a counter. A decoder adjusts the delay provided by the first delay path in response to a signal from the counter, until the delayed clock signals are in a locked state.

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