G - Physics – 06 – F
Patent
G - Physics
06
F
354/182
G06F 7/544 (2006.01)
Patent
CA 1245366
ABSTRACT A processing circuit comprises multiplication circuitry for successively multiplying a first input data signal by a second input data signal to produce a product signal representative of a result of multiplication and summing circuitry coupled to the multiplication circuitry for successively summing up said product signals a first predetermined number of times to produce a sum signal. Each of the first and second input data signals and the sum signal have a single precision bit length but each of the product signals has a double precision bit length. The summing circuitry includes a selector responsive to a selection signal for selecting the product signal or the sum signal. A shifter is provided for shifting each product signal towards the least signi- ficant bit of each product signal to produce a succession of shifted product signals each of which has the double precision bit length and for shifting the sum signal towards the most significant bit of the sum signal to produce a shifted sum signal. The summing circuitry also includes an accumulator for successively accumulat- ing the shifted product signals to produce a sum signal having the double precision bit length. An overflow monitor is provided for monitoring occurrence of an overflow in the shifted sum signal to process the shifted sum signal and thereby to produce a processed signal which has the double precision bit length.
513275
Kuroda Ichiro
Nishitani Takao
Sugishita Kyosuke
Tanaka Hideo
Corporation Nec
Smart & Biggar
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