G - Physics – 06 – F
Patent
G - Physics
06
F
354/226
G06F 12/08 (2006.01) G06F 9/38 (2006.01) G06F 12/10 (2006.01)
Patent
CA 1323701
PROCESSING OF MEMORY ACCESS EXCEPTIONS WITH PRE-FETCHED INSTRUCTIONS WITHIN THE INSTRUCTION PIPELINE OF A VIRTUAL MEMORY SYSTEM-BASED DIGITAL COMPUTER ABSTRACT A technique for processing memory access exceptions along with pre-fetched instructions in a pipelined instruction processing computer system is based upon the concept of pipelining exception information along with other parts of the instruction being executed. In response to the detection of access exceptions at a pipeline stage, corresponding fault information is generated and transferred along the pipeline. The fault information is acted upon only when the instruction reaches the execution stage of the pipeline. Each stage of the instruction pipeline is ported into the front end of a memory unit adapted to perform the virtual-to-physical address translation; each port being provided with means for storing virtual addresses accompanying an instruction as well as means for storing corresponding fault information. When a memory access exception is encountered at the front end of the memory unit, the fault information generated therefrom is loaded into the storage means and the port is prevented from accepting further references.
611918
Firstenberg Mark A.
Fite David B.
Fossum Tryggve
Hetherington Ricky C.
Manley Dwight P.
Digital Equipment Corporation
Smart & Biggar
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