G - Physics – 06 – F
Patent
G - Physics
06
F
354/221
G06F 7/38 (2006.01) G11C 19/00 (2006.01)
Patent
CA 1173967
ABSTRACT A digital signal processing apparatus adapted for use with high speed multipliers, which multipliers are known in the prior art. Digital signal processing, in general, is based upon multiplication, summing, subtraction and storing of digital data. Besides multiplication, these functions are performed in the prior art by a large number of integrated circuits resulting in cost, power consumption and reliability problems. The processing register of the present invention performs the remaining arithmetic operations of sum- ming, subtraction, delay and storing of digital data while providing a plurality of different operating modes to accommodate a host of different applications. In order to accommodate different modes, the processing register comprises a memory storage register and a computation register which are under the control of a control register, which register accepts a control word input having bits thereof indicative of a particular mode of operation.
414639
Chitsaz Sirus
Krisher Dale L.
International Standard Electric Corporation
Smart & Biggar
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