G - Physics – 06 – F
Patent
G - Physics
06
F
G06F 11/16 (2006.01) G06F 11/00 (2006.01) G06F 11/14 (2006.01) G06F 11/20 (2006.01) G06F 11/18 (2006.01) G11C 29/00 (2006.01)
Patent
CA 2059143
A computer system has a plurality of processing units connected via one or more system buses. Each processing unit has three or more processors on a common support board and are controlled by a common clock unit. The three processors perform the same operation and a fault in a processor is detected by comparison of the operations of the three processors. If one processor fails, the operation can continue in the other two processors of the processing unit at least temporarily, before replacement of the entire processing unit. Furthermore, the processing unit may have a plurality of clocks within the clock unit, with a switching arrangement so that the processors normally receive clock pulses from a main clock, but receive pulses from an auxiliary clock if the main clock fails. Switching between the main and auxiliary clock involves a comparison of the pulse duration from the clocks. Additionally, a plurality of cache memories may be connected in common to the processors so that failure of one cache memory permits the processing unit to continue to operate using the other cache memory. Coherence of the contents of the cache memories may be achieved by direct comparison, and a comparison method can also be used to invalidate data in an internal cache memory of a processor which differs from that in the external cache memory. Coherence of protocols may also ensure that data in caches of the different processor units are always correct.
Araoka Manabu
Fukumaru Hiroaki
Iijima Saburou
Kanekawa Nobuyasu
Kaneko Shigenori
Hitachi Ltd.
Hitachi Process Computer Engineering Inc.
Kirby Eades Gale Baker
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