Processor-based smart packet memory interface

Details Processor-based smart packet memory interface Processor-based smart packet memory interface

H - Electricity

04

L

H04L 29/10 (2006.01) G06F 15/16 (2006.01) H04L 29/06 (2006.01)

Patent

CA 2110134

PROCESSOR-BASED SMART PACKET MEMORY INTERFACE ABSTRACT A processor-based packet memory interface for controlling the transfer of data between multiple communications channels and packet memory in a communications adapter is presented, where the communications adapter uses requestor IDs to identify transmit and receive processes. The processor-based packet memory interface is controlled by a microprocessor configured to perform read and write operations with the communications adapter. The microprocessor is further configured to reserve a plurality of blocks of memory in the packet memory so that the number of communications channels that can be supported is not limited to the number of requestor ID's that can be handled by the communications adapter. The processor-based packet memory interface also includes RAM, for use by the microprocessor, to store pointers to reserved blocks of memory in the packet memory and to temporarily store packet data for transfer between the communications channels and the communications adapter.

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