Processor controlled interface with instruction streaming

Details Processor controlled interface with instruction streaming Processor controlled interface with instruction streaming

G - Physics

06

F

354/230.8

G06F 12/12 (2006.01) G06F 9/38 (2006.01) G06F 12/08 (2006.01)

Patent

CA 1332248

PROCESSOR CONTROLLED INTERFACE WITH INSTRUCTION STREAMING ABSTRACT OF THE DISCLOSURE A processor controlled interface between a processor, instruction cache, and main memory provides for simultaneously refilling the cache with an instruc- tion block from main memory and processing the instruc- tions in the block while they are being written to the cache.

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