Processor design for extended-precision arithmetic

Details Processor design for extended-precision arithmetic Processor design for extended-precision arithmetic

G - Physics

06

F

G06F 7/38 (2006.01) G06F 19/00 (2006.01)

Patent

CA 2327924

A processor for performing a multiply-add instruction on a multiplicand A, a multiplier B, and an addend C, to calculate a result D. The operands are double-precision floating point numbers and the result D is a canonical-form extended-precision floating point number having a high order component and a low order component. The processor is a fused multiply-add processor with a multiplier, an adder, a normalizer and a rounder. The post-adder data path, the normalizer and the rounder each have a data width sufficient to represent post-adder intermediate results to permit the high and low order words of a correctly-rounded result D to be computed. The mantissas of the extended-precision result D are provided such that the high order word mantissa is stored to double precision registers.

Affiliated with

Also associated with

Rating

Processor design for extended-precision arithmetic does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Processor design for extended-precision arithmetic, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Processor design for extended-precision arithmetic will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFCA-PAI-O-1658617