Processor for constrained least squares computations

Details Processor for constrained least squares computations Processor for constrained least squares computations

G - Physics

06

F

354/160

G06F 7/38 (2006.01)

Patent

CA 1294366

22762-530 ABSTRACT A processor is provided which is suitable for constrain- ed least squares computations. It incorporates a systolic array of boundary, internal, constraint and multiplier cells arranged as triangular and rectangular sub-arrays. The triangular sub-array contains boundary cells along its major diagonal and connected via delays, together with above-diagonal internal cells. It computes and updates a OR decomposition of a data matrix X incorporating successive data vectors having individual signals as elements. The rectangular sub-array incorporates constraint cell columns each implementing a respective constraint vector and terminating at a respective multiplier cell. The constraint cells store respective conjugate constraint factors obtained by constraint vector transformation in the triangular sub-array. Rotation para- meters produced by OR decomposition in the triangular sub-array are employed by the rectangular sub-array to rotate a zero input and update stored constraint factors. Cumulative rotation of this input and summation of squared moduli of constraint factors are carried out in cascade down constraint columns. The boundary cells are arranged for cumulative multiplication of cosine rota- tion parameters. Multiplier cells multiply cumulatively multi- plied cosine parameters by cumulatively rotated constraint column inputs and divide by summed squared moduli of constraint factors to provide residuals. Each constraint column produces respective residuals in succession corresponding to weighting of the data matrix X to produce minimum signals subject to a respective con- straint governing the form of weighting, as required to compute minimum variance distortionless response (MVDR) results.

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