Processor performance counter for sampling the execution...

G - Physics – 06 – F

Patent

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G06F 11/30 (2006.01) G06F 11/34 (2006.01)

Patent

CA 2231570

A processor includes an execution pipeline and a retire unit coupled to an end of the execution pipeline. The processor executes instructions of a program. An apparatus for collecting performance data while the instructions are executing includes a register coupled to the retire unit of the processor. Means are provided for incrementing the register whenever an instruction is retired from the execution pipeline. In addition the apparatus includes means for generating an interrupt to an interrupt handler whenever the register is incremented to a predetermined value.

L'invention est un processeur comportant un pipeline d'exécution et une unité d'extraction couplée à l'une des extrémités de ce pipeline d'exécution. Ce processeur exécute les instructions d'un programme. Un appareil de saisie de données de performance pendant l'exécution de ces instructions est doté d'un registre couplé à l'unité d'extraction du processeur. Un dispositif incrémente le contenu du registre chaque fois qu'une instruction est extraite du pipeline d'exécution. L'appareil de l'invention comprend de plus un dispositif servant à produire un signal d'interruption qui est transmis à un programme de gestion des interruptions chaque fois que le contenu du registre atteint une certaine valeur prédéterminée.

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