Processor with means to address operands in microinstructions

G - Physics – 06 – F

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354/230.7

G06F 9/00 (2006.01) G01R 31/3185 (2006.01) G06F 7/00 (2006.01) G06F 7/57 (2006.01) G06F 9/22 (2006.01) G06F 9/26 (2006.01) G06F 9/35 (2006.01) G06F 9/46 (2006.01) G06F 9/48 (2006.01) G06F 11/07 (2006.01) G06F 12/08 (2006.01) G06F 12/14 (2006.01) G06F 15/00 (2006.01)

Patent

CA 1174767

ABSTRACT A data processing system having a flexible internal structure, protected from and effectively invisible to users, with multilevel control and stack mechanisms and capability of performing multiple, concurrent operations, and providing a flexible, simplified interface to users. The system is internally comprised of a plurality of separate. independent processors, each having a separate microinstruction control and at least one separate. independent port to a central communications and memory node. The communications and memory node is an independent processor having separate. independent microinstruction control and comprised of a plurality of independently operating, microinstruction controlled processors capable of performing multiple, concurrent memory and communications operations. Addressing mechanisms allow permanent. unique identification of information and an extremely large address space accessible and common to all such systems. Addresses are independent of system physical configuration. Information is identified to bit granular level and to information type and format. Protection mechanisms provide variable access rights associated with individual bodies of information. User language instructions are transformed into dialect coded, uniform. intermediate level instructions to provide equal facility of execution for all user languages. Operands are referred to by uniform format names which are transformed, by internal mechanisms transparent to users, into addresses.

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