G - Physics – 06 – F
Patent
G - Physics
06
F
G06F 7/48 (2006.01) G06F 7/50 (2006.01) G06F 7/52 (2006.01) G06F 7/544 (2006.01)
Patent
CA 2269868
Multipliers 107 through 110 carry out an multiplication operation with two data out of the four data transferred from a memory over buses 101 through 104. The multiplication results are subjected to an addition or subtraction operation with each other in adder-subtracters 111 and 112. The operation results obtained by the adder-subtracters 111 and 112 are supplied to adders 113 and 114 where they are added to values held by accumulators 115 and 116. A latch circuit 105 supplies the data transferred through the bus 102 to the multiplier 109 when a control signal 106 indicates "ON". The latch circuit 105 temporarily holds the data transferred through the bus 102 and supplies the data held therein to the multiplier 109 when a control signal 106 indicates "OFF".
Corporation Nec
Smart & Biggar
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