G - Physics – 11 – C
Patent
G - Physics
11
C
G11C 16/04 (2006.01) G06F 7/00 (2006.01) G06F 12/00 (2006.01) G06F 12/14 (2006.01) G06F 21/00 (2006.01) G11C 7/10 (2006.01) G11C 7/24 (2006.01) G11C 8/20 (2006.01) G11C 16/22 (2006.01) G06F 1/00 (2006.01)
Patent
CA 2310080
A memory device (100) comprises a memory array (102) having corresponding first access control bits (202, 204) to control access thereto. A second set of access control bits (104) is provided to control write access to the first access control bits. The memory array is divided into memory blocks, each block having a corresponding access control bit. At least one such block (BLK0) is further subdivided into pages, each page having a corresponding control bit.
L'invention porte sur un dispositif mémoire (100) comprenant une matrice (102) possédant des premiers bits (202, 204) de commande d'accès correspondants qui permettent de commander l'accès à cette matrice. Un second ensemble de bits (104) de commande d'accès permet de commander l'accès d'enregistrement aux premiers bits de commande d'accès. La matrice de la mémoire est divisée en blocs, chacun de ces blocs possédant un bit de commande d'accès correspondant. Au moins un bloc (BLK0) est en outre divisé en pages, chacune de ces pages possédant un bit de commande correspondant.
Cromer Daryl C.
Maletsky Kerry D.
Pruett Gregory
Steinmetz Michael J.
Ward James P.
Atmel Corporation
Smart & Biggar
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