Programmable broadband input/output processor

Details Programmable broadband input/output processor Programmable broadband input/output processor

G - Physics

06

F

G06F 13/10 (2006.01) G06F 15/177 (2006.01) H04L 12/56 (2006.01) H04Q 7/30 (2006.01)

Patent

CA 2372395

A programmable broadband input/output processor (60) includes a memory (66) to store configuration data, a radio receive First-In-First-Out circuit (84), and a radio transmit First-In-First-Out circuit (74). A processor core (72) is connected to the memory (66), the radio receive First-In-First-Out circuit (84), and the radio transmit First-In-First-Out circuit (74). The processor core (72) selectively receives subsets of the configuration data based upon parameters associated with data in the radio receive First-In-First-Out circuit (84) and the radio transmit First-In-First-Out circuit (74). Page address First-In-First-Out circuits (62, 64) are also connected to the processor core (72). A communication bus (46) connected to the processor core (72) selectively relays control information to and from a central site station (42).

L'invention concerne un processeur d'entrée/sortie à large bande programmable (60) équipé d'une mémoire (66) servant à stocker les données de configuration, d'un circuit (84) récepteur premier entré premier sorti (FIFO) et d'un circuit émetteur (74) premier entré premier sorti (FIFO). Un noyau du processeur (72), connecté à la mémoire (66), au circuit (84) et au circuit (74), reçoit de manière sélective des sous-ensembles de données de configuration d'après les paramètres associés aux données dans le circuit (84) et le circuit (74). Des circuits adresse de pages (62, 64) premier entré premier sorti sont aussi connectés au noyau du processeur (72). Un bus de communication (46) connecté au tore (72) assure un relais sélectif des informations de commande vers et de la station centrale (42).

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