Programmable coding and decoding arrangement

Details Programmable coding and decoding arrangement Programmable coding and decoding arrangement

H - Electricity

04

M

354/67

H04M 3/26 (2006.01) H04B 14/04 (2006.01) H04B 17/00 (2006.01)

Patent

CA 1216068

Abstract of the Disclosure A coding and decoding arrangement situated between and connected to digital and analog telecommunication lines includes a plurality of signal processing components which are arranged in respective receive and transmit paths and which process incoming digital signals and convert them into analog signals, and convert outgoing analog signals into digital signals and process the latter. A plurality of multiplexers is provided, each arranged ahead of one of the components in the respective receive and transmit path, and having respective test paths connected thereto. The multiplexers can be switched by control signals such as to selectively form test routes through the arrangement, each test route including a different combination of the components, so that testing signals can be sent through such components via the test routes for testing the performances of such components. An additional multiplexer is arranged at the ends of the test routes and is operative for selectively connecting such test routes to an output of the arrangement. The control signals are applied to control inputs of the multiplexers and selected combinations thereof are stored in respective memory locations of a test memory, to be called therefrom upon addressing of the respective memory location. The memory locations of the test memory are addressed by a test latch which is connected to a data bus carrying the respective address of the memory location to be addressed. The test latch is enabled by a signal issued by an externally controlled address decoder.

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