Programmable data path width in a programmable unit having...

Details Programmable data path width in a programmable unit having... Programmable data path width in a programmable unit having...

G - Physics

06

F

354/166

G06F 9/30 (2006.01)

Patent

CA 1267441

ABSTRACT OF THE DISCLOSURE A processing system including an arithmetic logic unit having various functional units. The system comprises a first level subinstruction storage means, a second level subinstruction storage means, and a control register. The first level subinstruction storage means contains first level subinstructions which include an address to the second level subinstruction storage means. The first level storage means also includes second level subinstructions which contain control signals. The second level subinstruction storage means contains other second level subinstructions which have control signals contained therein. The control register is coupled to the first level subinstruction storage means and the second level subinstruction storage means to receive second level subinstruction control signals from one or the other of the storage means. The control register is further coupled to the arithmetic logic unit to supply the control signals to the various functional units of the arithmetic logic unit.

554741

Affiliated with

Also associated with

Rating

Programmable data path width in a programmable unit having... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Programmable data path width in a programmable unit having..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Programmable data path width in a programmable unit having... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFCA-PAI-O-1225619