Programmable data path width in a programmable unit having...

Details Programmable data path width in a programmable unit having... Programmable data path width in a programmable unit having...

G - Physics

06

F

354/166, 354/230

G06F 9/30 (2006.01) G06F 9/22 (2006.01) G06F 9/26 (2006.01) G06F 9/318 (2006.01)

Patent

CA 1256579

-30- ABSTRACT OF THE DISCLOSURE A processor is disclosed having two levels of subinstructions, each stored in its own memory with the lower level memory containing only a limited set of such lower level instructions with the rest of the lower level instructions that are desired to be used being supplied by the code stream from the upper level memory. The processor data bus is selectable as either a 16 bit or 32 bit wide bus under programmable control. ,

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