Programmable fault insertion arrangement and method

Details Programmable fault insertion arrangement and method Programmable fault insertion arrangement and method

G - Physics

01

R

324/58.1

G01R 31/28 (2006.01)

Patent

CA 2022239

A PROGRAMMABLE FAULT INSERTION ARRANGEMENT AND METHOD ABSTRACT A method for controlling a fault insertion circuit is disclosed that is arranged to generate and apply a fault signal to a digital circuit under test. First, a prompt request command is transmited to the fault insertion circuit from the data terminal. The fault insertion circuit receives the prompt request command and transmits to the data terminal a hardware fault response character if a hardware fault has been detect- ed, or a configuration status response character. An insertion command and fault instruction data is trans- mitted to the fault insertion circuit from the data terminal in response to the configuration status re- sponse character. The fault insertion circuit receives the insertion command and fault instruction data and ascertains if the insertion command and the data instruction are valid. If the command or the instruction are invalid, then an appropriate invalid command response character is transmitted to the data terminal. When the insertion command and instruction data are valid, the fault insertion circuit induces a fault to the digital circuit under test in accordance with the parameters of the data instruction. Finally, a completed response character is transmitted to the data terminal from the fault insertion circuit when the insertion command is successfully completed. 17

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