Programmable logic array

Details Programmable logic array Programmable logic array

H - Electricity

03

K

328/137

H03K 19/088 (2006.01) H03K 17/693 (2006.01) H03K 19/177 (2006.01) H03K 19/21 (2006.01)

Patent

CA 1204171

PROGRAMMABLE LOGIC ARRAY Abstract of the Disclosure A single plane programmable logic array (PLA) using dynamic CMOS logic has switching transistors located at specific locations within a row-column matrix. The transistors within a column are series connected and have their gates common connected in rows. PMOS and NMOS control transistors conduct exclusively to connect output and input ends of the columns respectively to logic 1 or logic 0 in successive phases of a common clock. Control inputs are applied to specific rows. By applying data inputs to column input ends and interconnecting all the column output ends, the PLA is configured to function as a multiplexer. By setting the input end of columns to logic 0 and selectively interconnecting output ends of the columns, the PLA is configured to perform other combinational logic functions.

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