Programmable logic array adder

Details Programmable logic array adder Programmable logic array adder

G - Physics

06

F

354/204

G06F 7/50 (2006.01)

Patent

CA 1103359

PROGRAMMABLE LOGIC ARRAY ADDER ABSTRACT This specification discloses a multi digit binary adder embodied in programmable logic arrays (PLAs). The particular programmable logic array used here has a separate two bit decoder for receiving each like order pairs of digits Ai, Bi of two n digit binary numbers A0, A1....An-1 and Bo, B1....Bn-1 plus a carry Cin. The decoders generate an output signal called a min term on a different line for each of the four possible combinations AiBi, Ai?i, ?iBi and ?i?i of the true and complement of each pair. The min terms from the decoders are fed to an array called the product term generator or AND array which generates product terms fP = f0(A0,B0) f1(A1,B1)....fn-1(An-1,Bn-1) fn(Cin) The product terms are fed to a second array called a sum of product term generator or OR array that sums product terms fp. A series of latches is last in the sequence of logic elements making up the PLA. These latches each perform an AND function to generate a sum bit Si that is an AND of two functions supplied by the OR array to the inputs of the latches to generate a sum S0, S1....Sn-1 plus a carry Cout for the adder at the output of the PLA. The adder is optimized for a PLA with latches that perform an AND function.

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