Programmable logic array with single clock dynamic logic

Details Programmable logic array with single clock dynamic logic Programmable logic array with single clock dynamic logic

H - Electricity

03

K

328/128

H03K 19/177 (2006.01) G11C 7/00 (2006.01) H03K 19/096 (2006.01)

Patent

CA 1260560

ABSTRACT Disclosed is a programmable logic array employing dynamic CMOS logic and utilizing a single clock signal and its complement to synchronize said dynamic logic operations. The PLA disclosed employs two logic planes for implementing arbitrary logic equations on input logic signals. The first logic plane and second logic plane are evaluated on separate phases of a clock signal and its complement and are separated by a clocked latch/inverter for providing correct logic evaluation between the logic planes.

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