Programmable microprocessor booting technique using fifo memory

Details Programmable microprocessor booting technique using fifo memory Programmable microprocessor booting technique using fifo memory

G - Physics

06

F

G06F 12/08 (2006.01) G06F 9/38 (2006.01) G06F 9/445 (2006.01)

Patent

CA 2097874

A computer system includes a host computer and at least one programmable slave processor boots the slave processor simply and inexpensively by using a first in first out (FIFO) memory connected between the host computer and the slave processor. Specifically, the computer system includes a host computer, a programmable microprocessor (the slave processor) controlled by the host computer, a FIFO memory connected between the host computer and the microprocessor, and means for providing a boot program and/or boot data from the host computer to the microprocessor through the FIFO memory. When the boot program functions, operating instructions for the microprocessor are read into the microprocessor's own random access memory (RAM).

L'invention est un système informatique comportant un ordinateur hôte et au moins un processeur esclave programmable qui est amorcé de façon simple et peu coûteuse au moyen d'une mémoire premier entré premier sorti (FIFO) montée entre l'ordinateur hôte et lui-même. Plus exactement, le système informatique de l'invention comprend un ordinateur hôte, un microprocesseur programmable (le processeur esclave) contrôlé par l'ordinateur hôte, une mémoire FIFO montée entre l'ordinateur hôte et le microprocesseur, et un dispositif servant à fournir au microprocesseur un programme d'amorçage et/ou des données d'amorçage provenant de l'ordinateur hôte par l'intermédiaire de la mémoire FIFO. Quand le programme d'amorçage est en fonction, les instructions d'exploitation à l'intention du microprocesseur sont obtenues de la mémoire vive (RAM) du microprocesseur même.

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