G - Physics – 06 – F
Patent
G - Physics
06
F
354/1, 354/230.3
G06F 3/00 (2006.01) G05B 19/08 (2006.01) G06F 13/00 (2006.01)
Patent
CA 1042555
PROGRAMMABLE SOLID STATE CONTROL FOR MACHINE TOOL OR PROCESS CONTROL SYSTEMS Abstract of the Disclosure A programmable signal processor having solid state compon- ents which can be programmed to duplicate the control functions of an electromechanical relay panel. The processor includes an AND memory matrix having a plurality of individual inputs and outputs which are connectible through diodes to outputs of solid state gated input memories and through jumpers to inputs of solid state gated feedback memories. The input memories have inputs which are switched by external inputs to the pro- cessor. The feedback memories are switched by outputs of the AND memory and provide input signals to the AND memory which simulate the signals provided by normally closed and normally open contacts of a relay. The outputs of the AND memory are selectively connected through wire jumpers to the inputs of the feedback memories and circuits which control the outputs of the processor so the feedback memories and output circuits of the processor will switch in response to outputs from the memory in an OR logic manner. The combination of the AND logic functions provided by the AND memory and the OR logic functions provided by the Jumpers permits the processor to be programmed using Boolean logic equations or directly pro- grammed from a conventional relay schematic or ladder diagram without using special programming language. A two phase clock provides output signals which causes all of the input memories to switch simultaneously in response to changes in the exter- nal inputs to the processor to eliminate races between the switching of the input memories. The clock also causes all of the feedback memories to switch simultaneously in response to changes in the outputs of the AND memory to eliminate races between the instants of switching of the feedback memories. The instants of switching of the input memories and the feedback memories are out of phase to eliminate races between the input signals and the feedback signals within the processor and the processor to operate with greater noise immunity.
244728
Dix James A.
Eckl James J.
Na
Square D. Company
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