Programmer for implanted pacer

Details Programmer for implanted pacer Programmer for implanted pacer

G - Physics

08

C

326/1, 354/22

G08C 19/22 (2006.01) A61N 1/37 (2006.01) A61N 1/372 (2006.01)

Patent

CA 1117217

Abstract A plurality of programming bits are placed into a parallel in-serially out register. When the programmer is activated, a monostable resets a counter, and energizes an oscillator which clocks the counter. Three subintervals from the counter are utilized for pulse width modulation of the programing signals. Once for each bit, the output is energized and begins transmitting pulses at the lowest subinterval rate. Depending upon the logic state of each bit, the transmission pulse is terminated either at the second or the third sub- interval time.

309558

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