Protection apparatus for multiple processor systems

Details Protection apparatus for multiple processor systems Protection apparatus for multiple processor systems

G - Physics

06

F

354/224

G06F 11/00 (2006.01) G06F 13/18 (2006.01)

Patent

CA 1143849

Case 04-4212-U.S. APPLICATION OF STEVEN A. ROSE AND EDWARD H. FORRESTER PROTECTION APPARATUS FOR MULTIPLE PROCESSOR SYSTEMS ABSTRACT In a data protection apparatus for a multiple CPU system having a common or multiported bulk memory, an interface structure is associated with each of the CPU's. The interface structure cooperates with a firmware engine which is, in turn, a part of the interface control means which controls the transfer of data between the common bulk memory apparatus and each of the several CPU's in the system. Signals generated by the individual CPU's indicative of an emergency situation are applied as input signals to the interface structure. The interface structure then translates those signals into an attention flag signal and signals identifying the source or nature of the emergency. The firmware engine then responds to those signals and effects the necessary measures to protect the data relative to the affected CPU.

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