Protection of analog reference and bias voltage inputs

Details Protection of analog reference and bias voltage inputs Protection of analog reference and bias voltage inputs

H - Electricity

01

L

328/200

H01L 27/092 (2006.01) H01L 27/02 (2006.01) H02H 7/00 (2006.01)

Patent

CA 1314946

ABSTRACT A latchup and electrostatic discharge protection circuit for an analog reference or bias voltage power supply input connected between an input power providing terminal of the power supply and a power rail of a CMOS integrated circuit having a parasitic latch device. The protection circuit comprised of three field effect transistors close-circuits a path from the power supply input to the power rail for normal power supply conditions and open-circuits the path for excessively positive and negative voltages at the power supply input, thereby safeguarding the CMOS integrated circuit from currents resulting from the excessive positive and negative voltages.

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