Protection system for critical memory information

Details Protection system for critical memory information Protection system for critical memory information

G - Physics

06

F

G06F 12/16 (2006.01) G07B 17/00 (2006.01)

Patent

CA 2072504

?270 - 1340/17013 ABSTRACT A computer system, typically a postage meter system, has a processor, a memory, an address decoder, and a window circuit. The window circuit selectively couples the write strobe output of the processor with the write strobe input of the memory in response to the processor's setting and clearing of a latched signal. A counter resets the processor if the latched signal is is set and not cleared within a predetermined time period.

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