Providing current control over wafer borne semiconductor...

Details Providing current control over wafer borne semiconductor... Providing current control over wafer borne semiconductor...

G - Physics

01

R

G01R 31/27 (2006.01) G01R 31/28 (2006.01) G01R 31/316 (2006.01)

Patent

CA 2457685

Disclosed are methods for providing wafer parasitic current control to a semiconductor wafer (1240) having a substrate (1240), at least one active layer (1240) and at least one surface layer (1240), Current control can be achieved through the formation of patterns ( 1240) surrounding contacts (1215), said patterns (1240) including insulating implants and/or sacrificial layers formed between active devices represented by said contacts (1215). Current flows through active regions (1260) associated with said contacts (1215) and active devices. Methods of and systems for wafer level burn-in (WLBI) of semiconductor devices are also disclosed. Current control at the wafer level is important when using WLBI methods and systems.

L'invention concerne des procédés destinés à produire une commande de courant parasite pour une tranche de semi-conducteur (1240) comprenant un substrat (1240), au moins une couche active (1240) et au moins une couche superficielle (1240). La commande de courant peut être réalisée par formation de motifs (1240) entourant des contacts (1215), lesdits motifs (1240) comprenant des implants d'isolation et/ou des couches sacrificielles formées entre des dispositifs actifs représentés par ces contacts (1215). Le courant traverse les zones actives (1260) associées à ces contacts (1215) et à ces dispositifs actifs. L'invention concerne également des procédés et des systèmes de déverminage au niveau de la tranche (WLBI) de dispositifs à semi-conducteurs. La commande de courant au niveau de la tranche est importante lorsqu'on utilise des procédés et des systèmes WLBI.

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