Pseudo-dual port memory having a clock for each port

Details Pseudo-dual port memory having a clock for each port Pseudo-dual port memory having a clock for each port

G - Physics

11

C

G11C 7/10 (2006.01) G11C 7/22 (2006.01)

Patent

CA 2633889

A pseudo-dual port memory (1) has a first port, a second port, and an array of six-transistor memory cells (19). A first memory access is initiated upon a rising edge of a first clock signal (ACLK) received onto the first port. A second memory access is initiated in response to a rising edge of a second clock signal (BCLK) received onto the second port. If the rising edge of the second clock signal occurs within a first period of time, then the second memory access is initiated immediately following completion of the first memory access in pseudo-dual port fashion. If the rising edge of the second clock signal occurs later within a second period of time, then the second memory access is delayed until after a second rising edge of the first clock signal. The durations of the first and second memory accesses do not depend on the duty cycles of the clock signals.

L'invention porte sur une pseudo-mémoire double port comprenant un permier port, un second port et un réseau de cellules mémoire à six transistors. Un premier accès mémoire est déclenché sur le flanc montant d'un premier signal d'horloge reçu au premier port. Un second accès mémoire est déclenché en réponse à un flanc montant d'un second signal d'horloge reçu au second port. Si le flanc montant du second signal d'horloge se produit dans les limites d'une première période de temps, le second accès mémoire est alors déclenché immédiatement après que se soit terminé le premier accès mémoire en mode pseudo-double port. Si le flanc montant du second signal d'horloge se produit plus tard, dans les limites d'une seconde période de temps, le second accès mémoire est retardé jusqu'après un second flanc montant du premier signal d'horloge. Les durées du premier et du second accès mémoire ne dépendent pas des rapports cycliques des signaux d'horloge.

Affiliated with

Also associated with

Rating

Pseudo-dual port memory having a clock for each port does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Pseudo-dual port memory having a clock for each port, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Pseudo-dual port memory having a clock for each port will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFCA-PAI-O-1642972