Pseudo-noise sequence generator

Details Pseudo-noise sequence generator Pseudo-noise sequence generator

H - Electricity

03

K

328/97

H03K 3/84 (2006.01)

Patent

CA 1282463

Abstract of the Disclosure A pseudo-noise sequence generator includes a memory which is accessed by a (2n+m)-bit address signal and outputs a parallel n-bit pseudo noise sequence prestored at a corresponding address, and n registers for delaying each bit of the parallel n-bit output signal from the memory by one clock. The (2n+m)-bit address signal consists of a parallel n-bit digital input signal, the outputs from the n registers, and an m-bit control signal.

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