Pseudo set-associative memory cacheing arrangement

Details Pseudo set-associative memory cacheing arrangement Pseudo set-associative memory cacheing arrangement

G - Physics

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354/244

G06F 12/08 (2006.01) G06F 12/02 (2006.01)

Patent

CA 1301367

PSEUDO SET-ASSOCIATIVE MEMORY CACHEING ARRANGEMENT Abstract of the Invention The invention provides a pseudo set-associative memory cacheing arrangement for use in a data processing system comprising a processor interfacing to a main memory and adapted to support a cache memory. The arrangement comprises a plurality of cache memory banks each comprising a respective number of addressable locations individually defined by a cache address. A plurality of cache select circuits are each associated with a respective one of the cache memory banks and each one is responsive to m most significant bits of a main memory address and control signals for mapping its associated cache memory bank to a predetermined range of addresses in main memory. - i -

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