Pseudo-static memory subsystem

Details Pseudo-static memory subsystem Pseudo-static memory subsystem

G - Physics

11

C

354/241

G11C 11/34 (2006.01) G11C 11/406 (2006.01) G11C 11/4076 (2006.01)

Patent

CA 1275150

PSEUDO-STATIC MEMORY SUBSYSTEM Abstract of the Disclosure A memory subsystem comprises pseudo-static memory chips operable in a low power self refresh mode or in a standby mode in which less access time is required. All memory chips are initially placed in the self refresh mode and are changed to the standby mode only when individually accessed. Then, the accessed chip is retained in the standby mode until such time as all chips are periodically returned to the self refresh mode. When a memory chip is first changed to the standby mode a delay time is provided to allow for the greater required access time. Thereafter, the memory chip which have then been placed in the standby mode are tracked by latching of addresses and comparison of the latched addresses to subsequently received addresses.

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