H - Electricity – 03 – L
Patent
H - Electricity
03
L
325/1, 343/60, 3
H03L 5/00 (2006.01) H03K 17/10 (2006.01) H03K 17/687 (2006.01) H03K 17/691 (2006.01)
Patent
CA 1273412
Abstract of the Disclosure A low level input pulse signal from T2L logic is delivered to the input of a ground deck driver which is transformer-coupled to a floating deck driver. The leading edge of the input pulse serves to enable or trigger a first FET driver, which is coupled to the gates of a plurality of series-connected FETs via a first transmission line transformer. The triggering of the FET driver serves to turn-on the series-connected FETs so that the same delivers a high voltage signal to an output load. A second FET driver is coupled to the gates of another plurality of series-connected FETs, which serve as a "tail-biter" to terminate the power to the output load. And, a third FET driver is coupled to the gates of the first-mentioned series-connected FETs to turn the same to the OFF state. The second and third FET drivers are coupled to their respective series-connected FETs via respective transmission line transformers. The trailing edge of the input trigger pulse enables the second and third FET drivers to concurrently turn-on the tail-biter FETs and turn-off the first-mentioned, series-connected FETs.
537170
Jones Franklin B.
Kerfoot Charles S.
Milberger Walter E.
Aspila Kalevi P.
Government Of The United States Of America As Represented By The
Government Of The United States Of America Represented By The Se
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