Pulse width modulated self-clocking and self-synchronizing...

Details Pulse width modulated self-clocking and self-synchronizing... Pulse width modulated self-clocking and self-synchronizing...

H - Electricity

04

L

H04L 7/027 (2006.01) H03K 7/08 (2006.01) H03K 9/08 (2006.01) H04L 7/06 (2006.01) H04L 12/00 (2006.01) H04L 25/49 (2006.01)

Patent

CA 2041222

Transmissions of synchronous digital data from a master control unit (50A) to a slave, network termination unit (50B) are via a pulse width modulated data stream including pulse width modulated binary code pulses (20, 22) with a pulse width modulated synchronization pulse (24) all of which have a preselected leading edge transition (28) at the same point in each cycle of a master clock signal. A clock signal is derived at the network termination unit (50B) from the received pulse width modulated binary data stream for decoding and for nonself- clocking, synchronous transmissions from the slave, network termination unit (50B) to the master, control unit (50A). The phase synchronization pulse (24) is employed to maintain phase synchronization between the transmission to and from the control unit (50A).

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