Quadruple word, multiplexed, paged mode and cache memory

Details Quadruple word, multiplexed, paged mode and cache memory Quadruple word, multiplexed, paged mode and cache memory

G - Physics

06

F

354/241

G06F 12/00 (2006.01) G06F 12/08 (2006.01)

Patent

CA 2016683

QUADRUPLE WORD, MULTIPLEXED, PAGED MODE AND CACHE MEMORY Abstract of the Disclosure A 64 bit wide memory is multiplexed over a 32 bit data bus to provide data to a 64 bit line size cache memory controlled by an 82385 cache controller. The memory addresses to all 64 bits of memory are held during the entire transfer so that a zero wait state second 32 bit transfer occurs. Logic develops the necessary next address and ready pulses and blocks these signals from the cache controller. Logic also handles the bit 2 address for the main and cache memories. The main memory is operated in paged mode to further increase system performance.

Affiliated with

Also associated with

Rating

Quadruple word, multiplexed, paged mode and cache memory does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Quadruple word, multiplexed, paged mode and cache memory, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Quadruple word, multiplexed, paged mode and cache memory will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFCA-PAI-O-1827767